? october 2003 - revision 1.3 (working document) 1/11 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. VNQ810PEP quad channel high side driver target specification (*) per each channel n cmos compatible inputs n open drain status outputs n on state open load detection n off state open load detection n shorted load protection n undervoltage and overvoltage shutdown n loss of ground protection n very low stand-by current n reverse battery protection (**) description the VNQ810PEP is a monolithic device designed in stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). active current limitation combined with thermal shutdown and automatic restart protects the device against overload. the device detects open load condition both in on and off state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. type r ds(on) i out v cc VNQ810PEP 160 m w (*) 5 a (*) 36 v block diagram (**) see application schematic at page 8 overtemp. 1 v cc gnd input1 output1 overvoltage logic driver 1 status1 v cc clamp undervoltage clamp 1 openload on 1 current limiter 1 openload off 1 output3 input2 status2 output2 output4 control & protection equivalent to channel1 input3 status3 input4 status4 input2 status2 v cc control & protection equivalent to channel1 input3 status3 v cc control & protection equivalent to channel1 input4 status4 v cc powersso-24 order codes package tube t&r powersso-24 VNQ810PEP VNQ810PEP13tr
2/11 VNQ810PEP absolute maximum rating connection diagram (top view) symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v p tot power dissipation t c =25c 66 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c current and voltage conventions 1 2 3 4 5 6 7 8 9 10 output1 output1 output2 output2 input2 input3 status3 status2 gnd v cc 11 12 24 23 22 21 20 19 18 17 16 15 14 13 input1 status1 input4 status4 n.c. v cc output2 output3 output3 output4 output4 output4 output1 output3 i s i gnd v cc gnd v cc outputn i outn v outn inputn i inn statusn i statn v inn v statn ta b = v cc
3/11 VNQ810PEP thermal data (*) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m m thick). horizontal mounting and no artificial air flow. electrical characteristics (8v 8v 160 320 m w m w i s supply current off state; v cc =13v; v in =v out =0v off state; v cc =13v; v in =v out =0v; t j =25 c on state; v cc =13v; v in =5v; i out =0a 20 20 8.5 60 40 13.5 m a m a ma i l(off1) (**) off state output current v in =v out =0v 0 50 m a i l(off2) (**) off state output current v in =0v; v out =3.5v -75 0 m a i l(off3) (**) off state output current v in =v out =0v; v cc =13v; t j =125c 5 m a i l(off4) (**) off state output current v in =v out =0v; v cc =13v; t j =25c 3 m a symbol parameter test conditions min typ max unit t d(on) turn-on delay time r l =13 w from v in rising edge to v out =1.3v 30 m s t d(off) turn-off delay time r l =13 w from v in falling edge to v out =11.7v 30 m s dv out / dt (on) turn-on voltage slope r l =13 w from v out =1.3v to v out =10.4v see relative diagram v/ m s dv out / dt (off) turn-off voltage slope r l =13 w from v out =11.7v to v out =1.3v see relative diagram v/ m s symbol parameter test conditions min typ max unit v il input low level 1.25 v i il low level input current v in = 1.25v 1 m a v ih input high level 3.25 v i ih high level input current v in = 3.25v 10 m a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in = 1ma i in = -1ma 66.8 -0.7 8v v 1
4/11 VNQ810PEP electrical characteristics (continued) v cc - output diode status pin protections openload detection symbol parameter test conditions min typ max unit v f forward on voltage -i out =0.5a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v stat status low output voltage i stat = 1.6 ma 0.5 v i lstat status leakage current normal operation; v stat = 5v 10 m a c stat status pin input capacitance normal operation; v stat = 5v 100 pf v scl status clamp voltage i stat =1ma i stat = - 1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload conditions t j >t tsd 20 m s i lim current limitation v cc =13v 5.5v < v cc < 36v 57.510 10 a a v demag turn-off output clamp voltage i out =1a; l= 6mh v cc -41 v cc -48 v cc -55 v symbol parameter test conditions min typ max unit i ol openload on state detection threshold v in =5v 20 40 80 ma t dol(on) openload on state detection delay i out =0a 200 m s v ol openload off state voltage detection threshold v in =0v 1.5 2.5 3.5 v t dol(off) openload detection delay at turn off 1000 m s 2 v inn v statn t dol(off) open load status timing (with external pull-up) v inn v statn over temp status timing t sdl i out < i ol v out > v ol t dol(on) t j > t tsd t sdl
5/11 VNQ810PEP t t v outn v inn 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on) switching time waveforms truth table conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l
6/11 VNQ810PEP iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results i ii iii iv 1c c c c 2c c c c 3acccc 3bcccc 4c c c c 5c e e e electrical transient requirements on v cc pin class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
7/11 VNQ810PEP figure 1: waveforms open load without external pull-up status n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc status n input n status n status n input n status n input n open load with external pull-up undefined overtemperature input n status n t tsd t r t j output voltage n v cc v ol v ol v cc >v ov
8/11 VNQ810PEP gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / i s(on)max . 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. application schematic v cc d ld +5v r prot outputn statusn inputn +5v gnd m c d gnd r gnd v gnd r prot
9/11 VNQ810PEP m c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l 10/11 VNQ810PEP pr e li mi nary powersso-24 ? mechanical data dim. mm. min. typ max. a 1.9 2.22 a2 1.9 2.15 a1 0 0.07 b 0.34 0.4 0.46 c 0.23 0.32 d 10.2 10.4 e7.4 7.6 e0.8 e3 8.8 g 0.1 g1 0.06 h 10.1 10.5 h 0.4 l 0.55 0.85 n 10o x3.9 4.3 y6.1 6.5
11/11 VNQ810PEP information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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